In recent years, trends in the microelectronic industry indicate that future multiprocessor chips may be composed of tens or even hundreds of nodes. A node can be a processing element, also called a core, and can refer to other electronic devices such as a cache, sensor, or memory. Typically, the nodes of a multiprocessor chip are integrated, share the same interconnects as the rest of the system, and each node processes and/or stores data independently. Multi-node chips packaged on a single die consume less power than the same nodes distributed in a different manner, such as on a circuit board. However, on-chip and off-chip communication between nodes of multi-node chips or across nodes on the same chip has emerged as an issue for sustaining performance growth and decreasing power consumption when processing computationally demanding, data-intensive applications. For example, computational bandwidth scales linearly with the growing number of data processing nodes, but the rate at which data can be communicated on-chip between nodes of a multi-node chip increases at a slower pace. In addition, the rate at which data can be communicated off-chip is also growing more slowly than compute bandwidth, and the energy cost of on-chip and off-chip communication significantly limits the achievable bandwidth. As a result, physicists and engineers continue to seek alternative systems for on-chip and off-chip, node-to-node communications.